Product Summary
The Digital Costas Loop (DCL) HSP50210JC-52 performs many of the baseband processing tasks required for the demodulation of BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM waveforms. These tasks include matched filtering, carrier tracking, symbol synchronization, AGC, and soft decision slicing. The DCL HSP50210JC-52 is designed for use with the HSP50110 Digital Quadrature Tuner to provide a two chip solution for digital down conversion and demodulation. The DCL HSP50210JC-52 processes the In-phase (I) and Quadrature (Q) components of a baseband signal which have been digitized to 10 bits. As shown in the block diagram, the main signal path consists of a complex multiplier, selectable matched filters, gain multipliers, cartesian-to-polar converter, and soft decision slicer.
Parametrics
HSP50210JC-52 absolute maximum ratings: (1)Supply Voltage: +7.0V; (2)Input, Output Voltage: GND -0.5V to VCC +0.5V; (3)ESD: Class 3; (4)Voltage Range: +4.75V to +5.25V; (5)Temperature Range: H: 0℃ to +70℃; (6)Thermal Resistance (Typical) θJA℃/W: PLCC Package: 24; (7)Maximum Storage Temperature: -65℃ to +150℃; (8)Maximum Junction Temperature PLCC: +150℃.
Features
HSP50210JC-52 features: (1)Clock Rates Up to 52MHz; (2)Selectable Matched Filtering with Root Raised Cosine or Integrate and Dump Filter; (3)Second Order Carrier and Symbol Tracking Loop Filters; (4)Automatic Gain Control (AGC); (5)Discriminator for FM/FSK Detection and Discriminator Aided Acquisition; (6)Swept Acquisition with Programmable Limits; (7)Lock Detector; (8)Data Quality and Signal Level Measurements; (9)Cartesian-to-Polar Converter; (10)8-Bit Microprocessor Control - Status Interface; (11)Designed to Work With the HSP50110 Digital Quadrature Tuner; (12)84 Lead PLCC; (13)Pb-Free Available (RoHS compliant).
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
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HSP50210JC-52 |
Intersil |
IC DEMODULATOR COSTAS 84-PLCC |
Data Sheet |
Negotiable |
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HSP50210JC-52Z |
Intersil |
Up-Down Converters COSTAS DEMODULATOR 84 PLCC 52MHZ COM |
Data Sheet |
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