DsPIC33FJ256MC710-I/PT

Product Summary

The DSPIC33FJ256GP506-I/PT is a High-Performance, 16-Bit Digital Signal Controller. The device supports a variety of motor control applications, such as brushless DC motors, single and 3-phase induction motors and switched reluctance motors. The DSPIC33FJ256GP506-I/PT is also well-suited for Uninterrupted Power Supply (UPS), inverters, switched mode power supplies, power factor correction and also for controlling the power management module in servers, telecommunication equipment and other industrial equipment.

Parametrics

DsPIC33FJ256MC710-I/PT absolute maximum ratings: (1)Ambient temperature under bias: -40 to +85℃; (2)Storage temperature: -65 to +150℃; (3)Voltage on VDD with respect to VSS: -0.3V to +4.0V; (4)Voltage on any combined analog and digital pin and MCLR, with respect to VSS: -0.3V to (VDD + 0.3V); (5)Voltage on any digital-only pin with respect to VSS: -0.3V to +5.6V; (6)Voltage on VCAP/VDDCORE with respect to VSS: 2.25V to 2.75V; (7)Maximum current out of VSS pin: 300 mA; (8)Maximum current into VDD pin: 250 mA; (9)Maximum output current sunk by any I/O pin: 4 mA; (10)Maximum output current sourced by any I/O pin: 4 mA; (11)Maximum current sunk by all ports: 200 mA; (12)Maximum current sourced by all ports: 200 mA.

Features

DsPIC33FJ256MC710-I/PT features: (1)Modified Harvard architecture; (2)C compiler optimized instruction set; (3)16-bit wide data path; (4)24-bit wide instructions; (5)Linear program memory addressing up to 4M instruction words; (6)Linear data memory addressing up to 64 Kbytes; (7)83 base instructions: mostly 1 word/1 cycle; (8)Sixteen 16-bit General Purpose Registers; (9)Two 40-bit accumulators: With rounding and saturation options; (10)Flexible and powerful addressing modes: Indirect, Modulo and Bit-Reversed; (11)Software stack; (12)16 x 16 fractional/integer multiply operations; (13)32/16 and 16/16 divide operations; (14)Single-cycle multiply and accumulate: Accumulator write back for DSP operations; Dual data fetch; (15)Up to ±16-bit shifts for up to 40-bit data.

Diagrams